Well, just a bit over a week ago I finished the textbook right on schedule, December 31st. I figured it’d be good to write down my thoughts and advice for anyone looking to do something similar.

Before I start giving you advice, let me clarify exactly who this guide is for. This guide is for someone (hopefully you!) who has a goal, which as a prerequisite requires them to gain a lot more knowledge than they currently possess. Ideally, this person has examined all their options for knowledge acquisition, whether it be looking at Wikipedia articles, binging a lecture series or purchasing a Nautilus subscription, and has decided that their best option is the (rapid) consumption of a particular textbook. If you are simply reading a textbook for pleasure, this guide may be of less use to you.

One last thing before we get into step 1. While I say “speedrun”, I strictly mean on the macro scale. While going through a whole textbook in 2 months may sound fast, I still had to spend upwards of 200 hours studying in order to finish it. While there’s definitely more efficient ways to take notes and such, there’s no real shortcuts! This guide is just advice on how to do the work.

Step 1: Create Your Strategy:

This strategy is going to be what guides your studies throughout the entire textbook. Your strategy is a product of two things: pace, and depth. How much content do you need to cover a day, and how deeply you need to cover it? These two things together determine approximately how much time you’ll need to spend a day to stay on pace.

I recommend you start by determining your deadline and dividing the days you have by the amount of pages in the textbook to find how many pages you’ll need to get through a day. In my case, I needed to go through 12.2 pages a day so I set my goal at 13 pages a day. This gives me built in leeway for days I can’t finish all my pages.

After determining the amount of content you’ll need to cover a day you need to determine how thoroughly you’ll be covering the content. Are you going to take notes? Do you just need an intuitive grasp, or do you need to become quantitatively proficient with the material? Your answers to these questions are going to change how much time it takes you to cover the same content. Some people may be limited in the time they can give per day. In that case you’ll either need to compromise on depth, push back your deadline, or just find more time in the day.

My chosen strategy was governed by my goal, and yours will be too. I needed an intuitive grasp of these concepts as a prerequisite to thoughtfully designing analog ICs. I wanted to take thorough notes so that I could have a “reference guide” of sorts to quickly reintuit any forgotten concepts. And I could skip out on a thorough quantitative understanding (AKA doing the practice problems) because I was about to spend the next 3 months actually practicing the concepts; so I’d pick up the quantitative understanding while actually designing, instead of frontloading it.

With these choices, 13 pages took me 3-4 hours on average. Note that measuring content by pages leads to a highly variable workload. Some days I could finish my pages in less than an hour, and some days it took 8! This is why building in leeway is so important for maintaining consistency.

I’d like to take a second to discuss notetaking strategy. If you decide to take notes, it’s going to add time to how long you spend studying each day. But I truly believe it’s worth it if you need to hold on to these concepts for any real amount of time. I highly encourage you to take notes throughout the process.

Always remember that note taking should be an act of synthesis, not transcription. Read through a section once, intuitively grasp the concepts, and then write down how this thing works according to your newfound intuition. The equations governing this behavior tend to help with acquiring intuition as well as act as a sort of sanity check against your understanding (can you explain why each term is where it is?), but if you feel they don’t help feel free to skip writing them down. You can always find them online anyways. The important thing is that the knowledge goes from the textbook, into your head, and then on to your notebook in a form that is suited to how you think. Never skip the part where it goes into your head! I’ve found myself mindlessly copying down equation after equation from the book before, and it’s a bad habit and a waste of time.

The reason I take notes like this is because I know that I’m going to forget everything I learn from this textbook, probably multiple times. The point of going through the textbook is to intuit every concept at least once, and capture this intuition in my notebook. Then in the future when I need to understand this concept again it’s both easier and faster because

1. I’ve already intuited it once before (it gets easier everytime!).
2. I now have a personal reference manual which details the concept however is most natural to me, which ideally (if you’ve taken your notes well) will act as a ‘guide’ to quickly intuiting the concept.

If you choose not to take notes, I highly encourage you to constantly check your understanding and mental model of the concepts at hand against practice problems or the examples laid out by the book. It is far too easy to simply speed through the textbook and convince yourself you have adequately understood the concepts without seriously digesting the information.

Step 2: Set up your schedule

Once you’ve decided on your page count and learning strategy, you’ll need to set aside time to actually study those pages. This can be hard at first, since you may not know how long your pages will actually take (probably a lot longer than you’re expecting!).

I recommend setting time aside in the morning and studying first thing everyday. Right after you wake up is the least volatile time in most people’s schedule and will lend itself well to habit formation by incorporating studying into your morning routine. For me this meant pushing myself to wake up at 6 am so I could study for a couple hours before having to leave for class or work. This was a pretty big adjustment from my old schedule, but I think you’ll find the productivity gain is more than worth it. On days when I couldn’t finish my pages before leaving, the couple hours of head start meant I typically only had to do an hour of studying to finish my pages before going to bed.

I can’t understate the importance of having study be a part of your daily schedule. If you’re really not a morning person then maybe set aside a couple hours before going to bed or some fixed time in the afternoon. No matter when you choose to study, you should try to keep it at a fixed time and location if possible. This helps with habit formation, which is the key to sticking with difficult things for long periods of time. Anybody can use a lot of will power to study a lot for one day. Pretty much no one can do that everyday for months. By making studying a habit, you don’t need to use will power to force yourself to study. While the actual studying is never gonna be effortless, you won’t need to waste effort convincing yourself to start or to keep going.

Step 3: Execute

Once you’ve got your strategy and schedule set up, the only thing left is the execution. It’s best if you can enjoy the studying. I doubt I would’ve been able to do this if I didn’t find the subject matter enjoyable. Because I’m not gonna lie to you: this is gonna suck sometimes. There’s gonna be days where the pages are particularly brutal and you’re on hour 6 wondering why the hell you’re doing this to yourself. Here are some tips for getting through it:

1. Find out how you focus
   1. The same pages can take 1 hour or 6, and that depends on how intense your concentration is. Personally, I enjoy using a pomodoro like timer system, where I set a timer for 55 minutes of study, and then afterwards I set a 10 minute one for break. If you can hone your concentration, this process is gonna get a lot easier.
2. Always be ahead
   1. I already mentioned the idea of building leeway into your pages per day earlier. This buffer is what saves you on bad days. Some days I could drop to 8–9 pages without falling behind because I’d already built slack. So always stay ahead!
3. Have a priority list
   1. Some days the concepts are brutal or your focus just isn’t there, and your study time runs out. When that happens, you either find more time or fall behind (tip: don’t fall behind!). I find it helpful to know ahead of time what I’m willing to sacrifice or not to stay on schedule. School or work? Never. Sleep? 1-2 times a week tops. Time to work on other projects? Typically the first on the chopping block. Time with friends? Well I’ll still hang out, but I’m bringing the textbook.
4. Tell people what you’re doing!
   1. Talk about what you’re doing with those around you. See if you can get a friend or two to even do it with you. When the people around you are aware of your goal, you’ll be more likely to stick to it. Peer pressure and all that.
5. Keep your eyes on the prize
   1. Your goal needs to genuinely motivate you. To me, designing an analog IC is pretty badass, and keeping that image in my head made the daily grind easier to tolerate. On long days, I wasn’t studying just to finish pages. I was studying to bring myself ever closer to that goal. My advice for doing hard things? Find whatever it is you want, and romanticize the shit out of it. Create a vivid image in your head of where all this effort leads, and revisit it often. For me, it’s important that whatever I’m doing is beautiful to me in some way.

Step 4: Success! (What’s next?)

If you’ve made it this far, congrats! Now you can move on to whatever your actual goal was. For me, this means I can finally move on to actually designing my analog IC.

For those of you wondering if doing this would be worth it for you or not, I have no idea! But to help you decide, I’ll briefly describe how it went for me.

Outcome and things I would do differently

To be completely honest with you, I think some part of me was always hoping that going through this textbook would be a silver bullet for me. That I would finish the textbook, magically know everything there is to know about analog IC design, and immediately go on to design super impressive complicated circuits. Let’s be clear: this is not a silver bullet. Reading a textbook does not make you amazing at a subject.

What did happen however, is that I am now comfortably aware of just about every major aspect of analog IC design. Not an expert, maybe not even proficient, but aware.

Analog IC design is a wide discipline with many interacting factors, none of which are trivial. I think that the combination of breadth plus depth was what makes this subject such a good candidate for textbook learning: I was able to build a higher-resolution mental map of the subject then by just watching lectures or youtube videos alone. It served as a broad and reasonably thorough introduction to CMOS IC design, and I would strongly recommend this approach to anyone in a similar position.

If your textbook targets a very specific or narrow topic, however, the experience may differ enough from my own that I can’t confidently recommend for or against this approach.

I would have done two things differently:

1. I would have taken synthesis based notes from the very start, and been stricter about keeping them short. Transcription based notes take longer and are less effective. Getting better at note taking is what saved me a lot of time towards the end of the process.
2. I would have set aside a day a week for practice problems. I definitely underestimated the efficacy of doing problems. Actually working through problems related to the topics I’m learning would have been a great help for acquiring intuition and long term retention. And by just setting aside a day a week, where maybe I did 6 pages and then an hour or two of problem solving would have been a great help, while only adding ~4 days to my deadline.

So there it is! As far as project updates go, I’ve now moved on to learning XSchem and Magic for the schematic and layout process of analog IC design respectively. It looks like there are unfortunately some complications with analog ICs for TinyTapeout’s March shuttle, so I may need to wait until May to tape out. However, I’ll still be keeping my personal deadline at March.

Thanks for reading!

Unfortunately it’s pretty inaccessible. Most people don’t get to make an IC (AKA ‘tape out’) until they’re in a graduate program pursuing their masters or PHD. That’s a couple years away for me, and I don’t want to wait that long. So I’m gonna make one now.

The way I see it, there’s three main issues standing in my way:

1. Making an IC is expensive
2. I know jack shit about making analog ICs.
3. I’m a pretty busy person, and this could take a lot of time

I thought of this project for the first time when I ran into TinyTapeout. They’re a business which crowdfunds production runs of ICs. For just a couple hundred dollars you can buy a tile on their chip and use the on-chip multiplexer to select your design. For a 2x2 analog tile IC with a couple pins, it’s gonna run me $700. That’s still a tough cost for a college student but definitely feasible. So there it is: I can afford my own tapeout (and you can too!) Now how am I going to actually make this thing?

I did some research and found a good looking textbook, Design of Analog CMOS Integrated Circuits by Behzad Razavi. People had a lot of praise for it online, so I figured if I went through this thing a little every day, and finished by the end of December, that’d give me 3 months to design an IC before TinyTapeout’s shuttle deadline in March. And I thought that seemed like a pretty decent plan.

So late October I did the math and realized I could finish that whole text book by January if I went through just 13 pages every day. Sounds easy right? Yeah that’s what I thought too. This stuff is dense. Some days it takes me 5-6 hours to go through those pages (one day it took me 10!) But my God has it worked. Before I started this, I didn’t even know how a MOSFET worked, let alone a whole op-amp. Now I’m definitely no expert, but I’m feeling pretty comfortable at the prospect of designing my own op-amp or bandgap reference.

The astute among you may have noticed I claimed to be busy, and yet somehow spend up to 10 hours studying this textbook every day. What gives? Well for starters, anything greater than 5 hours is pretty rare. Most days I can knock my pages out in around 3-4 hours. But I definitely didn’t have 3-4 spare hours with my schedule back in October. So I had to make time. Let’s not be too dramatic though. I just made two simple changes:

1. I started getting up at 6-7am everyday.
2. I got rid of Reddit, YouTube, Instagram, all the little distractions that were stealing my time.

And that was enough! This let me study my 13 pages every day first thing, and by skipping out on digital distractions, I’d made enough time to still do everything else I had to do. Combined with Pomodoro timers, I’d say I’m pretty efficient nowadays.

So that’s the plan! I’m going to keep studying this textbook everyday until I finish it on December 31st, and then I’m going to design an analog IC in 3 months. Of course I’ll post updates here as I move along. Wish me luck!

A couple of months back I decided to try making an analog function generator. My requirements were pretty loose, I just wanted to see if I could generate some square, triangle, and sine waves. Additionally, I wanted to be able to adjust the frequency and amplitude of the waves generated. This actually turned out to be pretty easy, only taking three op-amps.

The problem with this circuit is that it’s extremely limited in its bandwidth. This is because of the capacitors used in the integrators for the sine and square waves. As the frequency of the waveform rises, the capacitor presents less and less impedance so the waveform travels ‘around’ the op-amp via the capacitor. This causes the amplitude to drop, as the op-amp is what’s responsible for amplifying the waveform. Thus, our output waveform drops as our frequency rises. Pretty undesirable for a waveform generator.

What is an AGC? Why a Gilbert cell?

So our problem is that as the frequency rises, the op-amps become increasingly shorted. One way to stop this would be to swap the capacitors so that they present a higher impedance at higher frequencies. Or we could even swap out the amplifier topology entirely to circumvent this issue.

Another way would be to simply generate the signal, and then amplify the signal back to a desirable level afterwards. This method doesn’t involve modifying our current waveform generation circuit but instead adds another stage entirely. This stage would be responsible for amplifying the generated waveform so that it maintains a constant amplitude, in our case 5 volts peak-to-peak.

So for this secondary stage we have an input signal (the output of the function generator), which will have a varying amplitude. To maintain a constant amplitude we must apply a dynamic gain in order to respond to the variations in input amplitude. This process is known as automatic gain control (AGC). In this post we’ll begin by implementing a voltage controlled amplifier (VCA), which is an amplifier whose gain varies with a control voltage. In order to go from a VCA to AGC, we’ll need to implement a feedback loop to dynamically adjust this control voltage such that a constant output amplitude is maintained, although I won’t be discussing that in this post.

This is not a typical application for an AGC. To be honest, simply changing the function generator topology would be a better way to achieve a function generator with a desired output range and bandwidth. While the function generator is what got me started designing this AGC, at this point I am much more interested in designing a stand alone AGC whose capabilities would make it adequate for improving the bandwidth of the three op-amp function generator as well.

The rest of this post will discuss the design of the VCA; for which I’ve decided to use a Gilbert cell. It’s capable of multiplying voltages which means it’s capable of dynamic voltage controlled gain, and it’s also frequently used in RF applications which means it should be able to handle our desired frequency range of 1hz-1Mhz. Let’s first get an overview of how a gilbert cell works.

How does a gilbert cell work?

A gilbert cell is composed of 3 differential pairs. To keep everyone on the same page, I’ll quickly cover how a differential pair works. For those who already know, feel free to skip the next three paragraphs.

A differential pair is a differential amplifier which consists of two input transistors ending in a shared tail. Unlike single ended amplifiers, differential amplifiers take in two inputs and amplify the difference between them. The differential pair’s ‘tail’ is typically biased with a constant current and inputs are supplied at the base of either transistor. This difference in the input voltages causes the transistors to carry different amounts of current, however the sum of the current in either branch will always equal the bias current.

So in essence a differential pair takes in a voltage differential and outputs a current differential proportional to the input. By attaching load resistors at the output we are able to convert this differential current back into a differential voltage signal at the output node. The differential gain of this circuit can described by

$A_v = -g_m \cdot R_L$

Where $R_C$ is the load resistance placed at the collector. The transconductance ($g_m$) of a transistor is found by $I_c/V_t$ where $I_c$ is the current through the collector of the transistor and $V_t$ is the thermal voltage, approximated at 25mV. These equations mean that we can vary the gain of our differential pair by varying the current through the transistors! If we increase the bias current the gm increases with it and as a result the gain does as well. Similarly, if we decrease the bias current, we can reduce the gain. This allows us to change the gain. While a simple differential pair would be a viable candidate to create a VCA, there is an alternative topology which boasts a better frequency response.

The gilbert cell is typically found as a mixer in radio frequency applications. It consists of three differential pairs, two on the top layer and one on the bottom.

Let’s start by looking at the top two differential pairs. There’s only two things you really need to notice to understand how these work.

1. The two pairs are wired inversely of each other. This means that for any given input differential, $V_{in}$, one pair will receive $+V_{in}$ and the other will receive $-V_{in}$.
2. Their outputs are joined together such that their currents sum at the output.

Because the differential pairs receive inputs equal in magnitude but opposite in direction, their output current will also be equal in magnitude and opposite in direction. That means if both pairs are biased with an equal tail current, the output current will always be zero.

This is where the bottom differential pair comes in: By placing the top differential pairs as the ’load’ of each leg of the bottom differential pair, we are able to steer the current from one of the top differential pairs to the other, making the gain either more positive or negative depending on which load differential pair we drive more current through. Notably, the output of the gilbert cell will always be zero if either of its inputs are zero and the output itself is proportional to the product of the two input voltages. This is, loosely speaking, a multiplication of two voltages!

You may notice that sometimes the bottom ’tail’ of the differential pairs are split or joined throughout this post. They’re functionally equivalent to each other, although they respond differently to mismatch between components. The split style responds better to differential pair transistor mismatch which is why I’ve opted for it in the design.

Biasing the Gilbert Cell

The goal when biasing a gilbert cell is to ensure that all transistors stay in the active region for the desired input and output ranges while maximizing the voltage headroom for the output signal. We’ll be using a resistor tree in order set the dc operating point for our differential pairs. In our case we have to account for the voltage drop of four things:

• The current sink
• The bottom differential pair
• The top two differential pairs
• The load resistors

The transistors require, at minimum, a voltage of 0.2 volts between the collector and emitter to stay in their active region so we’ll need to ensure $V_{CE}$ > 0.2 volts throughout the input and output range. Otherwise, the transistor will saturate and we’ll risk cutting off or otherwise distorting the output waveform.

Let’s start by looking at the bottom differential pair. We know that $V_{CE}$ must be greater than 0.2 volts at all times during normal operation. We also know that our input will be fed to the base of the transistor and that $V_{BE}$ will always be around 0.6-0.7 volts. So, as the base voltage moves in unison with our input, we know $V_{E}$ will move with it as well, merely level shifted by -0.6 volts.

Since our input and emitter voltage move in unison, we must bias our bottom differential pair with exactly how much voltage we desire for our input range. In our case, I chose ±2 volts. This means we’ll need to bias our bottom differential pair so that it has 2 volts in either direction, so we’ll have 4 volts of voltage headroom dedicated towards the bottom differential pair. Throwing in the voltage drop required by the current mirror below the bottom differential pair, we end with a headroom cost of 5 volts. we can bias our bottom differential pair at 5 volts above our negative supply, which in our case is -4 volts.

Let’s look at biasing the top two differential pairs now. Just like the bottom differential pair, $V_{BE}$ will remain at 0.6-0.7 volts throughout normal operation. However, due to the extra input differential pair (explained later), the input to the top differential pair only varies by <0.1 volts and so $V_{E}$ does not move appreciably. It is therefore negligible for biasing purposes. This is also why we did not have to concern ourselves with the movement of $V_{C}$ for our bottom differential pair as the two are shorted.

While our top differential pairs’ emitter voltage does not move appreciably, their collectors are tied directly to both $V_{out}$ and our load resistors. This means, similar to in the bottom differential pair, their collecter voltage moves in unision with their respective output node. This relation is described by $-I_{1,2}R_L$ where $I_{1,2}$ represents the current for each of the top two branches. We must bias the top level differential pairs so that even when an output node is at its minimum allowable value the transistors still maintain a $V_{CE}$ > 0.2 volts. In our case the maximum desired output swing is 11 volts. Adding 0.3 volts to ensure a $V_{CE}$ greater than 0.2v leaves us with a bias value of 11.3 volts below $V_{CC}$. Because our circuit runs on a ±9V supply this means the top differential pairs are biased at -2.3 volts.

How do we ensure that at our max input range the load resistor will be dropping 11 volts? Knowing that $V_{out} = V_{CC}-IRL$ and that $I_{max} \cdot R_L = 11$ we know that $R_L = 11/I_{max}$ will ensure we drop 11 volts when our inputs are each at max. In our case, each leg of the bottom differential pairs is biased with 1ma and therefore $I_{max} = 2mA$. So, $R_L$ = 5.5k.

With this, we’ve ensured that the bottom and top differential pairs will avoid collector-emitter saturation for our desired input and output range. While biasing the operating points allows us to avoid $V_{CE}$ saturation, it doesn’t prevent saturation due to current steering. For that, we turn our attention to a different technique.

Emitter Degeneration

While we no longer have to worry about collector-emitter saturation, we have yet to deal with saturation due to current steering. This occurs when all current flows through one branch. Let’s look at our bottom differential pair, which we’ve biased for an input range of ±2 volts. But what if it only took ±1 volt to get all current flowing through a branch? Then raising the input past 1 volt would no longer meaningfully affect the output and our waveform would appear “clipped” at the peaks or otherwise distorted.

To find the voltage level at which current steering saturation occurs, we calculate the voltage differential required to drive all current to one branch. This voltage represents the maximum meaningful input differential, and is a function of the bias current flowing through each transistor’s emitter and the effective resistance of the transistors.

$\Delta V_{in} = 2I_{e} \cdot r_{e}$

Where $I_e$ is the bias current flowing through each emitter and $r_{e}$ is the effective resistance of the emitter. $r_{e}$ is found by dividing the thermal voltage by emitter current, $V_t/I_e$. Approximating $V_t$ as 25 mV and knowing our emitter current bias is 1mA, $r_{e}$ = 25 Ohms. Without emitter degeneration it only takes 50mV to steer all current to one transistor! As you can imagine, such a limited input range would be impractical for our circuit.

This can be remedied by placing a resistor, $R_{e}$, in the tail of the differential pair. This is known as emitter degeneration. In doing so, the resistor is directly added to the effective resistance of the emitter yielding:

$\Delta V_{in} = 2I_e \cdot (r_e + R_{e}) \approx 2 I_e R_{e} \quad \text{when } R_{e} \gg r_{e}$

This allows us to change the input voltage required to steer all current to one branch. Naturally, this reduces the gain of the circuit as more voltage is required to steer the same amount of current, however it also results in increased linearity. This is because at the edges of our input range the gain actually reduces slightly, and by spreading this change out over a wider input range we “smooth out” the change in transconductance ($g_m$)

In our circuit, we desire a 2 volt differential required to swing all current to one branch. Knowing our bias current is 1mA for each transistor and using the equation above we can determine that this requires a 2k emitter resistor.

Why a separate differential pair input?

If emitter degeneration allows us to expand our input voltage range, why haven’t we used it for our top differential pairs? If you remember from when we determined the bias points for our transistors we found that because the base of the bottom pair’s transistors were being directly driven by the control voltage, the input range for the bottom pair had a one-to-one cost on the voltage headroom. While this was a feasible cost when it was just 4 volts, what about 11? Such a cost on headroom would only leave us with ±1 volts for our output signal. Pretty undesirable.

In order to allow us a large input range we’ll need to somehow avoid the one-to-one relationship between input voltage and the emitter voltage of the top transistors in our gilbert cell. To do this we’ll first put the input voltage through a differential pair in parallel with the gilbert cell, in effect “side-loading” the input range, decoupling our input signal from the emitter voltage of the top differential pairs. This side-loaded differential pair once again has access to 18 volts of voltage headroom, and can easily accommodate an input range of ±5.5 volts by way of a 5.5k emitter resistor.

How should we load the output of our input differential pair? One option would be resistors, however these would need to attenuate our signal to ± 50mV. This would demand precise resistor values and would also be sensitive to mismatch. If we overshoot ±50mV our gilbert cell will saturate and distort or clip at the output. If we undershoot ±50mV we diminish our gilbert cell’s output range. Another more appealing option is diode connected transistors.

Diode connected transistors are transistors which have had the collector and base shorted and therefore act like diodes (as the name might suggest.) The reason that a diode load is desirable is because its current depends exponentially on its forward voltage. Because of this, we can express a large change in current with a negligible change in voltage. In our case, we are able to express our desired maximum current swing in ~50mV.

Here’s another way to look at it: A differential pair converts a voltage ratio to a current ratio, and by doing so it converts our voltage signal to a current signal. When we use a resistive load, we are in effect converting that current signal back to a voltage signal at the output node. However by using a diode connected load we maintain the signal as a current. Because transistors are effectively current controlled current sources we are still able to achieve adequate amplification despite a small input voltage swing as long as the current swing is large enough. One other notable benefit of a diode connected load is that by maintaining a relatively constant voltage across the input signal range, the early effect is greatly reduced and there is a reduction in non-linearity.

In conclusion, by conditioning our top input voltage before passing it to the top two differential pairs, we are able to expand the input voltage range while avoiding a costly reduction in the output range of the gilbert cell. One final note is that this input differential pair is capacitively coupled to the top two differential pairs of the gilbert cell. This method of coupling has a few drawbacks to it which will be discussed later. Ideally, it would be best to directly couple these two stages.

Current Biasing

For our current source, I opted for a slight modification of a basic current mirror. A basic current mirror topology consists of a NPN transistor with its collector and base shorted. This creates a ‘self-biasing’ transistor, which sets its own base voltage and current. This voltage and current are dependent on how much current flows through its collector. Then, by connecting this node to other transistors’ bases we can ensure that they also pass that much current through their collector, in essence ‘copying’ the current from our reference branch.

You might notice there is a transistor wired in between the collector and base of the transistor in our reference branch. That’s because I’ve implemented a current mirror technique known as base-current compensation. The new transistor is responsible for supplying the base current to the mirror transistors. In doing so, it reduces the error between the copied current branches and the reference branch by a factor of its beta.

The resistors placed below each current sink transistor are responsible for emitter degeneration. Their purpose is twofold.

1. They stabilize the output current by increasing the output resistance of each current sink and providing negative feedback at the emitter node.
2. They also allow us to modulate the amount of current sunk by each branch by changing their value. Our circuit is designed so that at 1k ohms the transistor sinks 1mA, however if we dropped the emitter resistor of any branch to 500 ohms instead the transistor would then sink 2 mA.

As for bias current, I’ve opted for 1mA. This was done to minimize the power dissipation of the circuit and our circuit still provides a moderate gain. The transistors used have the highest hfe when biased with 10mA, however this would come with 10 times increased power cost. I believe that in the future increased open-loop gain will be a necessity and the bias current is one area to look at.

Frequency analysis

I ran a frequency analysis in LTSpice. The results were better than I expected for a first pass at the circuit! The -3dB point lies at ~5MHz which far surpasses the desired bandwidth. The unity gain point occurs at ~44MHz. You might notice the ‘ramp up’ at the lower frequencies only reaching our peak gain at ~20kHz. This is because the input differential pair is capacitively coupled to the gilbert cell and is one reason motivating a future move to direct coupling. However for a general purpose broadband AGC, I believe this frequency response is acceptable.

SFDR Analysis

SFDR (Spurious Free Dynamic Range) is a metric which lets you see how ‘pure’ a waveform is. It’s the difference in amplitude, in decibels, between the desired output frequency and the largest undesired output frequency (known as a spur). In our case the SFDR with a max input range sine wave is ~30dB. This is pretty bad! For adequate audio, the minimum SFDR is somewhere around 50-60 dB and anything below this will sound audibly distorted.

I believe the cause for distortion is the nonlinearity which comes with using the full range of a differential pair. One potential modificiation would be lowering the input range and increasing gain so that we can stay closer to the quiescent current of the differential pair, where the gain is more linear. For now I ran another fourier transform with a smaller input wave, only 5 volts pk2pk. The SFDR increased to ~50dB, which isn’t amazing but definetly better.

Conclusion and Next Steps

The Good:

• It works!
  • I’m pretty pleased this thing works at all, even if it’s going to need quite a bit of tweaking before being ready for integration into an AGC feedback loop.
• The upper cutoff frequency is quite good
  • The upper bandwidth far exceed my expectations, easily clearing the 1Mhz desired.

The Bad:

• The lower cutoff frequency is quite bad
  • Due to the capacitive coupling between the input differential pair and the Gilbert cell, the lower cutoff frequency is much higher than the targeted 1Hz. A move to direct coupling in future revisions of this circuit will likely resolve this issue.
• Very low SFDR
  • The circuit is currently distorting input signals quite a bit. I have a suspicion this is due to the variance in $g_m$ across a differential pairs input range. Using less of the input range seems to alleviate this somewhat, however this alone is not satisfactory.
  • It’s possible the variations in voltage across the current sinks or the diode connected loads in the input differential pair are contributing to distortion as well.
• The gain is low
  • For a negative feedback loop, the higher the open-loop gain better. With a maximum control voltage, this gilbert cell has a gain of less than 2!
  • This is mostly due to emitter degeneration. At the beginning of this project, I wasn’t familiar with how negative feedback loops worked.
  • I’m likely to raise the gain in the future by raising the current drawn by the current sinks, trading off with power dissipation. I’ll also likely reduce or remove the emitter degeneration for the bottom pair entirely.

Overall, I believe these results are quite promising for a first iteration of the circuit. I’m particularly pleased with the bandwidth of the circuit, and it would be nice to see even half the simulated bandwidth once built.

The next steps for this project involve designing the other components necessary for the feedback loop of the AGC, as well as addressing the shortcomings of the current revision of the Gilbert cell. For the AGC loop, we’ll need a means of sensing the output wave forms amplitude, and a means of modifying the control voltage in response to the change in output amplitude. While a simple peak detector can detect the output amplitude of a waveform, it does so at a limited frequency range, so a design with a wider frequency range will be needed. We’ll also need a way to compare this peak with a reference voltage (our desired amplitude). While an op-amp could work here, I’m also interested in seeing if any transistor based solutions fit the bill.

I’d also like to begin prototyping the Gilbert Cell. I’ve ordered some matched transistor pairs, and look forward to building it soon. I’ll probably start with some jumper wires for a first pass but I’d also like to design a PCB for this project.

If you’ve made it this far, thanks for reading! I really appreciate it. I love to talk about this kind of stuff so if you have any questions or feedback feel free to shoot me an email!

If you have questions, feedback, or just wanted to connect, feel free to reach out at lws.at.lws@gmail.com